OpenWrt - Hardware Table DD-Wrt - Hardware Table

Model

Version

Platform & Frequency

Flash

RAM

Wireless NIC

Switch

boot_wait

Serial

JTag

USB

Others

Status

Asus WL-500b

1

Broadcom 4710 @ 125MHz

4MB

16MB

Broadcom (mini-PCI)

BCM5325

on

No

No

1x v1.1

Parallel

Supported

Asus WL-500g Deluxe

Broadcom 5365 @ 200MHz

4MB

32MB

Broadcom (integrated)

in CPU

on

Yes

No

2x v2.0

Supported

Asus WL-500g Premium

1

Broadcom 4704 @ 266MHz

8MB

32MB

Broadcom 4318 (mini-PCI)

BCM5325

on

Yes

No

2x v2.0

Supported

Asus WL-500g Premium

2

Broadcom 5354 @ 240MHz

8MB

32MB

Broadcom (integrated)

?

?

?

?

2x v2.0

WiP

Buffalo WHR-G54S

Broadcom 5352 @ 200MHz

4MB

16MB

Broadcom (integrated)

in CPU

on

Yes

Yes

Supported

Buffalo WHR-HP-G54

Broadcom 5352 @ 200MHz

4MB

16MB

Broadcom (integrated)

in CPU

Yes

Yes

VLAN GPIO

Supported

Buffalo WBR-G54(S)

Broadcom 4712 @ 200MHz

4MB

16MB

Broadcom (integrated)

ADM6996L

on

Yes

Yes

VLAN

Supported

Linksys WRT54GS

1.0

Broadcom 4712 @ 200MHz

8MB

32MB

Broadcom (integrated)

ADM6996L

off

Yes

Yes

VLAN GPIO

Supported

Linksys WRT54GS

1.1

Broadcom 4712 @ 200MHz

8MB

32MB

Broadcom (integrated)

BCM5325

off

Yes

Yes

Supported

Linksys WRT54GL

1.0 or 1.1

Broadcom 5352 @ 200MHz

4MB

16MB

Broadcom (integrated)

in CPU

off

Yes

Yes

VLAN

Supported

WL-500g Deluxe Mod
Add Serial : http:///showthread.php?t=1993
J5 - RST, 3.3V, UART_TX/RX1, UART_TX/RX2

wl500gx_serial_pcb.pdf

The difference between wl500g and wl500gx that the deluxe does not require a UART chip, so a simple RS232 transceiver will do. The parts you need: - 1 MAX3232 IC (SO-IC) - 5 1uF capacitors - cables, connectors You need to connect the router's 3.3v, GND, UART_TX0, UART_RX0 pins to the left side of the pcb, set the jumpers, and connect a DB9 connector to the right side.

and..
J1 - USB_3, USB_4, GPIO1, GPIO5, GPIO7

LinksysInfo and WRT54G.net.

http://wiki./OpenWrtDocs/NetworkInterfaces
Openwrt - Understanding Network Interfaces

http://wiki./OpenWrtDocs/Configuration
Openwrt - Network Configuration

http:///wiki/index.php/Tutorials
DD-WRT - Tutorial


GPIO information
http://wiki./OpenWrtDocs/Customizing/Hardware/MMC#WHRHPG54

VLAN configuration

LAN (vlan0), WAN (vlan1), DMZ (vlan2):
-vlan0ports="1 2 5*"
-vlan0hwname=et0
-vlan1ports="0 5"
-vlan1hwname=et0
-vlan2ports="3 4 5"
-vlan2hwname=et0
As of RC4, the switch is programmed and controlled by a set of switch modules (switch-core and switch-robo or switch-adm, depending on your hardware). These switch modules will create a /proc/switch/eth0, showing the current settings for the switch. The /proc/switch/eth0/vlan/0/ports is used the exact same way as the vlan0ports nvram variable, allowing you to change the switch settings in realtime.


Cisco-Linksys WRT54G
V1.0版，CPU型號Broadcom 4710 @ 125MHz，F(xiàn)lash=4M，RAM=16M，無線網(wǎng)卡使用Broadcom芯片的miniPCI卡
V1.1版，除了無線模塊改用Broadcom integrated外，并且增加了JTAG接口，基本上無其它區(qū)別；
V2.0版，在V1.1版本上將CPU改為Broadcom4712@200MHz，并且板子上有串口和JTAG接口，支持VLAN；
V2.2版，在V2.0上將交換機芯片由ADM6996L(支持VLAN)改為BCM5325，無其它區(qū)別；
V3.0版，配置同V2.2；
V3.1版，CPU主頻改為216MHz，其余同V3.0；
V4.0版，CPU改用Broadcom 5352@200MHz，CPU內(nèi)集成了交換機芯片，這樣就省掉了專門的交換機芯片，其余同V3.0；
V5.0版和V6.0版，F(xiàn)lash改為2M，RAM改為8M，其余同V3.0；（注意，F(xiàn)lash和RAM都小了，相當于配置降了）；
V7.0版，CPU與無線模塊都與6.0不同，CPU內(nèi)不含交換機芯片了，另外裝了枚ADM6996，無線模塊改用Atheros的了。
Cisco-Linksys WRT54GS
WRT54GS 1.0， Broadcom 4712 @ 200MHz （CPU），支持VLAN，8MB （Flash）32MB （RAM）Broadcom (integrated) （無線模塊）ADM6996L （Switch）
WRT54GS 1.1， Broadcom 4712 @ 200MHz 8MB 32MB Broadcom (integrated) BCM5325
WRT54GS 2.0， Broadcom 4712 @ 200MHz 8MB 32MB Broadcom (integrated) BCM5325
WRT54GS 2.1， Broadcom 4712 @ 200MHz 8MB 32MB Broadcom (integrated) BCM5325
WRT54GS 3.0， Broadcom 5352 @ 200MHz 8MB 32MB Broadcom (integrated) in CPU
WRT54GS 4.0， （注意，配置開始降了，與54G一樣了）Broadcom 5352 @ 200MHz 4MB 16MB Broadcom (integrated) in CPU
WRT54GS 5.0， （配置更低了）Broadcom 5352 @ 200MHz 2MB 16MB Broadcom (integrated) in CPU
WRT54GS 5.1， Broadcom 5352 @ 200MHz 2MB 16MB Broadcom (integrated) in CPU
WRT54GS 6.0， Broadcom 5352 @ 200MHz 2MB 16MB Broadcom (integrated) in CPU